(1) Field of the Invention
The present invention relates to a process used to fabricate a semiconductor device, and more specifically to a process used to fabricate a capacitor structure, for a random access memory, (DRAM), device.
(2) Description of the Prior Art
To achieve performance requirements for high density DRAM devices, stacked capacitor structures, featuring large surface areas, have been used. Stacked capacitor shapes, such as crown, or cylindrical shaped, structures, have allowed capacitance increases, resulting from increased capacitor surface area, to be realized, without increasing the lateral dimension of the capacitor, or without risking device reliability and yield, by decreasing the already thin, capacitor dielectric layer. However the use of crown, or cylindrical shaped, capacitor structures, arrived at by forming a crown shaped storage node, featuring large vertical shapes, can result in process difficulties when attempting to pattern the upper plate of the capacitor structure. The large vertical shapes, of the crown shaped storage node structure, present photolithographic patterning difficulties, in terms, of step height, critical image control, and mis-alignment.
This invention will describe a process for fabricating a DRAM, stacked capacitor structure, without the use of a specific photolithographic masking procedure, used with conventional processes, to create the capacitor upper plate structure, thus avoiding the difficulties in achieving critical dimension and correct alignment, in addition to the cost reduction realized via the reduction in a critical photolithographic masking step. The elimination of the upper plate, photolithographic procedure, is accomplished using a novel process sequence in the capacitor upper plate definition is achieved simultaneously with contact hole openings, made for bit line, capacitor, and substrate contact purposes, using one photolithographic mask, and using the same etching steps. The definition of the capacitor upper plate is made in an area in which the topography of a crown, or cylindrical shaped, storage node structure, is not present. The contact holes, opened in the polysilicon layer, used for the capacitor upper plate structure, are then lined with an insulator spacers, providing the necessary insulation between metal plug structures, in the contact holes, and the adjacent polysilicon upper plate structure. This process can be used for capacitor under bit line, (CUB), designs, as well as for capacitor over bit line, (COB), designs. Prior art, such as Yang et al, in U.S. Pat. No. 5,804,852, as well as Sun, in U.S. Pat. No. 5,648,291, show processes for creating capacitor under bit line structures, however these prior arts do not show the novel procedures, used in the present invention, such as the definition of the capacitor upper plate structure, during contact hole opening procedures.